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  datasheet differential spread spectrum clock driver mk1493-05 idt? differential spread spectrum clock driver 1 mk1493-05 rev f 010305 description the mk1493-05 is a spread-spectrum clock generator used as a companion chip with a ck410 system clock. the device is used in a pc or embedded system to substantially reduce electro-magnetic interference (emi). the device provides a differential spread-spectrum high frequency output and a reference output clock. an smbus is connected to the ck410 for command and control of the mk1493-05. the input reference clock to the mk1493-05 comes directly from the ck410. no external, expensive crystal or crystal oscillator is required. a 16-pin tssop package is employed to maximize board space utilization. features ? packaged in 16-pin tssop package ? available in pb (lead) free package ? single differential spread spectrum clock ? spread spectrum for emi control ? supports smbus index read/write and blocks read/write operations ? uses external 14.31818 mhz clock from ck410 ? low output jitter design ? power down mode lowers idd ? spread selection via hardware pins (down and center) block diagram control logic config. reg. clkout clkout iref pll clock synthesis sdata refout/sel 3 vss vdd clock buffer sclk clkin sel[3:1] spread spectrum circuitry 2 3 pwrdn
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 2 mk1493-05 rev f 010305 pin assignment spread spectrum selection table the spread enable and spread select[3:0] smbus register bits control spread modulation and enable/disable. the clkin clock input and ref clock output will not have or be spread. at device power-up the sp read-spectrum is enabled and hardware control is enabled. the s0 configuration bit is hard-coded to zero when hardware control mode is selected. 12 1 11 2 10 3 9 4 5 6 7 8 16 15 14 13 16 pin 173 mil (0.65mm) tssop clkin s3 s2 s1 pwrdwn ref/sel sclk sdata vdda vssa iref vssiref clkout clkout vss vdd s3 s2 s1 s0 spread % spread type 0000 0.8 down 0001 1.0 down 0010 1.25 down 0011 1.5 down 0100 1.75 down 0101 2.0 down 0110 2.5 down 0111 3.0 down 1000 + 0.3 center 1001 + 0.4 center 1010 + 0.5 center 1011 + 0.6 center 1100 + 0.8 center 1101 + 1.0 center 1110 + 1.25 center 1111 + 1.5 center
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 3 mk1493-05 rev f 010305 pin descriptions pin pin name pin type pin description 1 clkin input 14.31818 mhz single-ended clock input. 2 s3 input spread spectrum select pin #3. see table above. internal pull-down. 3 s2 input spread spectrum select pin #2. see table above. internal pull-down. 4 s1 input spread spectrum select pin #1. see table above. internal pull-down. 5 pwrdn input power down pin. active high. internal pulldown. 6 ref/sel i/o strap input for selecting clkout frequency and 14.31818 mhz reference clock. 7 sclk input smbus compatible clock. 8 sdata i/o smbus compatible data. 9 vdd power +3.3 v power supply for logic and outputs. 10 vss power ground for logic and outputs. 11 clkout output selectable 96/100 mhz spread spectrum differential clock output. 12 clkout output selectable 96/100 mhz spr ead spectrum differential clock output. 13 vssiref power ground for current reference. 14 iref input precision resistor attached to this pin is connected to the internal current reference. 15 vssa power ground for pll. 16 vdda power +3.3 v power supply for pll.
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 4 mk1493-05 rev f 010305 general smbus serial interface how to write: ? controller (host) sends a start bit ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the beginning byte location =n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n + x - 1 (see note 2) ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) sends a start bit ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the beginning byte location =n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address d5 (h) ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock sends byte n + x - 1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt(slave/receiver) tstartbit slave address d4 h) wr write ack beginning byte = n ack data byte count = x ack beginning byte = n . x b y t e ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt(slave/receiver) tstartbit slave address d4 (h) wr write ack beginning byte = n ack rt repeat start slave address d5 (h) rd read ack data bye count = x ack . x b y t e beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 5 mk1493-05 rev f 010305 smbus address the mk1493-05 is a slave-only device that supports block re ad and block write protocol using a single 7 bit address and read/write bit. a block write (d4h) or block read (d5h) is made up of seven (7) bits and one (1) read/write bit. the applications where the indexed block write and block are used, the dummy byte (bit 11-18) functions as a register-offset (8 bits) pointer. byte 0: control register a6 a5 a4 a3 a2 a1 a0 r/w# 1101010x bit description type power up condition output(s) affected notes 7 spread select 0 rw 0 clkout, clkout 1,2,3 6 spread select 1 rw s1 clkout, clkout 1,2,3 5 spread select 2 rw s2 clkout, clkout 1,2,3 4 spread select 3 rw s3 clkout, clkout 1,2,3 3 select output frequency, 1=100 mhz, 0=96 mhz rw sel 100/96 clkout, clkout 1,2 2 reserved, must be written as 0 rw 0 not applicable 1 1 spread spectrum enable, 0=spread off, 1=spread on rw 1=spread on clkout, clkout 1 0 hardware/software control of spread enable , s[3:0], and output frequency. 0=h.w cinttrol, 1=s/w control rw 0=h/w control not applicable
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 6 mk1493-05 rev f 010305 byte 1: control register byte 2 through 5: control bit description type power up condition output(s) affected notes 7 reserved, must be written as 0 r undefined not applicable 6 reserved, must be written as 0 r undefined not applicable 5 reserved, must be written as 0 r undefined not applicable 4 reserved, must be written as 0 r undefined not applicable 3 reserved, must be written as 0 r undefined not applicable 2 clkout enable, 0=disable, 1=enabled rw 1=enabled not applicable 1 reserved, must be written as 0 r undefined not applicable 0 reserved, must be written as 0 r undefined not applicable bit description type power up condition output(s) affected notes 7 to 0 reserved, must be written as 0 r undefined not applicable
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 7 mk1493-05 rev f 010305 byte 6: control register notes: 1. these bits are read-only when the hardware/software bit is set to hardware control. 2. when the hardware/software bit is set to hardware cont rol these bits reflect the state of the s[3:1 ] and sel100/96# pins and the so bit is set to zero. when the hardware/software bit is set to software control the s[3:1] and sel100/96# pins are overridden by these bits. 3. see spread spectrum selection table on page 2 for spread selection options. 4. use the same vendor id as is used for the ck408 clock chip. power down mode operation the power down pin is used to shut off the clock cleanly prior to shutting off power to the device. the power down pin is an active high asynchronous input. when pwrdwn is sampled low for two output clock periods then all clocks need to be stopped prior to turning off the vco. all clocks need to be stopped in a predictable manner. clkout is driven differentially when pwrdwn# is de-asserted unless the clkout is disabled through the smbus register bit. bit description type power up output(s) affected notes 7 revision id bit 3 r -- not applicable 6 revision id bit 2 r -- not applicable 5 revision id bit 1 r -- not applicable 4 revision id bit 0 r -- not applicable 3 vendor id bit 3 r -- not applicable 4 2 vendor id bit 2 r -- not applicable 4 1 vendor id bit 1 r -- not applicable 4 0 vendor id bit 0 r -- not applicable 4 clkout/ clkout clkin refout pwrdn clk vco on off tphz
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 8 mk1493-05 rev f 010305 clkin must have a stable clock input when pwrdn is de-asserted. if clkin starts after pwrdn is de-asserted then tstable specification applies to when cl kin is on. if clkin is full on before pwrdn is de-asserted then the tstable specification applies. clkout clkout/ clkin pwrdn/ de-a ssertion, clkin already running refout vdd clk vco pwrdn off starting stable tstable tpzh clkout/ clkout clkin pwrdn/ de-a ssertion, clkin not yet running refout vdd clk vco pwrdn off starting stable tstable tpzh
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 9 mk1493-05 rev f 010305 application information series termination resistor clock output traces should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitors as with any high-performance mixed-signal ic, the mk1493-05 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelin es should be observed. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) to minimize emi, and obtain the best signal integrity, the 33 ? series termination resistor should be placed close to the clock output. 3) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the mk1493-05. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the mk1493-05. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. exposure to ab solute maximum rating conditions for extended periods can affect product re liability. electrical parameters are guaranteed only over the recommended operating temperature range. item rating supply voltage, vdd, vdda 5.5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm)
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 10 mk1493-05 rev f 010305 electrical characteristics - dc unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c 1 includes 50k ohm internal. 2 single edge is monotonic when transitioning through region. 3 inputs with pull-ups/-downs are not included. 4 internal leakage to ground is less than equal to 5 ua to ensure high level if input is floating. 5 configuration is rr=475 ohms at 1%. iref=2.32 ma. iref=vdd/(3 x rr). electrical characteristics - clkin/refout unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c 1 measured from vdd/2. parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.465 input high voltage 2 v ih 2.0 vdd +0.3 v input low voltage 2 v il vss-0.3 0.8 v input leakage current 3 i il 0 < vin < vdd -5 5 a output high voltage 2 v oh i oh = -1 ma 2.4 v output low voltage 2 v oh i oh = 1 ma 0.4 v output current 5 ioh clkout, voh@z=0.7 v@50 ohms 6*iref +12% x i operating supply current i dd no load 55 ma i ddpd no load, input low 400 a input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf pin inductance l pin 5nh output resistan ce rout clkout 3.0 k ? pull-up resistor 1,4 rpu real time, asynchronous assertion 120 k ? pull-down resistor 1,4 rpd real time, asynchronous assertion 120 k ? parameter symbol conditions min. typ. max. units rise time t rise from 0.8 v to 2.0 v 600 1200 ps fall time t fall from 2.0 v to 0.8 v 600 1200 ps edge rate rising edge 1.0 4.0 v/ns edge rate falling edge 1.0 4.0 v/ns duty cycle 1 40 60 % jitter, cycle-to-cycle 1 1000 ps accuracy long term accuracy 300 ppm
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 11 mk1493-05 rev f 010305 electrical characteristics - clkout unless stated otherwise, vdd=3.3 v 5% , ambient temperature 0 to +70 c 1 test setup is rs=33.2 ohms, rp=49.9 ohms with 2 pf. 2 measurement taken from a single-ended waveform. 3 measurement taken from a differential waveform 4 measured at the crossing point where instantaneous voltages of both clkout and clkout/ are equal parameter symbol conditions min. typ. max. units high voltage 1,2 v h 660 700 850 mv low voltage 1,2 v l -150 0 mv crossing point voltage 1,2 absolute 250 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 80 ps modulation frequency spread spectrum 32.5 khz rise time 1,2 t rise from 0.175 v to 0.525 v. rising edge clkout and falling edge clkout/. 175 700 ps fall time 1,2 t fall from 2.0 v to 0.8 v 175 700 ps rise/fall time variation 1,2 125 ps rise/fall time matching 1,2 20 % duty cycle 1,3 45 55 % output voltage variation 1,2 undershoot, overshoot -0.3 vhigh+0. 3 v
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 12 mk1493-05 rev f 010305 electrical characteristics - ac unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c, c l = 15 pf 1 clkout and smbus pins are tri-stated when pwrdn/ is asserted. clkout is driven differential when pwrdn/ is de-asserted unless its already disabled. 2 the period is when vdd equals its typical vdd condition. measurement diagrams measurement diagram for duty cycle and jitter. current reference source (iref) if board target trace impedance (z) is 50 ? , then rr = 475 ? (1%), providing iref of 2.32 ma, output current (i oh ) is equal to 6*iref. thermal characteristics parameter symbol conditions min. typ. max. units output enable time 1 tpzl,tpzh all outputs 10 us output disable time 1 tplz,tphz all outputs 600 1200 ps stabilization time 2 tstable from power-up 3.0 ms spread change time tspread settling period after spread change 3.0 ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w high duty cycle % low duty cycle % 1.5v t period
mk1493-05 differential spread spectrum clock driver clock synthesizer idt? differential spread spectrum clock driver 13 mk1493-05 rev f 010305 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt rese rves the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature mk1493-05g 149305g tubes 16-pin tssop 0 to +70 c MK1493-05GTR 149305g tape and reel 16-pin tssop 0 to +70 c mk1493-05glf 149305gl tubes 16-pin tssop 0 to +70 c mk1493-05glftr 149305gl tape and reel 16-pin tssop 0 to +70 c mk1493-05gln 149305gn tubes 16-pin tssop 0 to +70 c mk1493-05glntr 149305gn tape and reel 16-pin tssop 0 to +70 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-4522 clockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com mk1493-05 differential spread spectrum clock driver clock synthesizer


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